1. Field of the Invention
The present invention generally relates to a nonvolatile semiconductor memory device such as an EPROM (erasable programmable read only memory), EEPROM (electrically erasable programmable read only memory) and a flash memory. The present invention also relates to a method of manufacturing such a nonvolatile semiconductor memory device.
2. Description of the Related Arts
High-density nonvolatile memory devices have been receiving much attention for application in many fields. One of the most important factors is the low cost of the reduced size of each memory cell. However, it is very difficult to shrink the cell size in the fabrication of nonvolatile memory cells when the conventional local oxidation (LOCOS) isolation technique is used. The isolation structure formed by this technique has a very large dimension and thus limits the miniaturization of the memory cells.
Another isolation technique called shallow trench isolation (STI) has been introduced to the fabrication of nonvolatile memory devices to reduce the cell size. The conventional field oxides are replaced by STI structures so that the device integration can be effectively improved. However, as component dimensions continue to shrink, the surface area of floating gates also shrinks. This leads directly to a decrease in capacitance of the effective capacitor formed between the floating gate layer and the control gate layer. This decrease in effective capacitance results in a reduction of the capacitive coupling ratio, which is a parameter that describes the coupling to floating gate of the voltage applied to control gate. The poorly-coupled voltage to floating gate limits the programming and accessing speed characteristics of the memory device.
The capacitive coupling ratio Cp is defined by:   Cp  =      Ccf          Ccf      +      Cfs      
where Ccf is capacitance between the control gate and the floating gate; and Cfs is capacitance between the floating gate and the semiconductor substrate.
In order to gain programming and accessing speeds in nonvolatile memories, many attempts have been done to increase the coupling ratio. It can be understood from the above equation that when the capacitance Ccf between the control gate and the floating gate increases, the coupling ratio Cp increases. Therefore, the coupling ratio Cp is generally increased by increasing the capacitor area between the floating gate and control gate, which increases the capacitance Ccf, and therefore the coupling ratio Cp. For example, U.S. Pat. No. 6,171,909 discloses a method for forming a stacked gate of a flash memory cell. The coupling ratio of the stacked gate is increased by forming a conductive spacer. The conductive spacer, which is a portion of the floating gate, increases the capacitor area between the floating gate and control gate.
In the present invention, a nonvolatile semiconductor memory device with an increased coupling ratio is disclosed. This is accomplished by providing a reduced size floating gate which reduces the capacitance Cfs between the floating gate and the semiconductor substrate. The effect is the same as increasing the capacitance Ccf between the control gate and the floating gate.
An object of the invention is to provide a nonvolatile semiconductor memory device having an increased capacitive coupling ratio.
Another object of the invention is to provide a nonvolatile semiconductor memory device having an reduced size floating gate with a gate width beyond lithography limit.
A further object of the invention is to provide a method for forming a nonvolatile semiconductor memory device having an increased capacitive coupling ratio.
A yet further object of the invention is to provide a method for forming a nonvolatile semiconductor memory device having an reduced size floating gate with a gate width beyond lithography limit.
An important feature of the invention is to provide two dielectric spacers on a pair of opposing sidewalls of xe2x80x9cRAISEDxe2x80x9d isolation structures that protrude over a substrate. The dielectric spacers effectively decrease the dimension of the floating gate as well as the floating gate width. This reduces the capacitance Cfs between the floating gate and the semiconductor substrate, and therefore, increases the capacitive coupling ratio.
According to an aspect of the invention, there is provided a nonvolatile memory device including two isolation structures protruding above a substrate; two dielectric spacers disposed on a pair of opposing sidewalls of the two isolation structures; a tunnel dielectric and a floating gate provided on the substrate and confined between the two dielectric spacers; and a control gate electrode formed on the floating gate with an inter-gate dielectric interposed therebetween.
According to another aspect of the invention, there is provided a nonvolatile memory device including two isolation structures protruding above a substrate; two dielectric spacers disposed on a pair of opposing sidewalls of the two isolation structures, the two dielectric spacers being spaced from one another at a distance that defines a gate width therebetween; a tunnel dielectric and a floating gate provided on the substrate and confined between the two dielectric spacers, the floating gate having a surface substantially coplanar with a surface of the isolation structures; and an inter-gate dielectric and a control gate formed on the coplanar surfaces of the floating gate and the isolation structures.
According a further aspect of the invention, there is provided a method for forming a nonvolatile memory device comprising the steps of forming two isolation structures protruding above a substrate; forming two dielectric spacers on a pair of opposing sidewalls of the two isolation structures; forming a tunnel dielectric layer and a floating gate layer on the substrate and confined between the two dielectric spacers on the substrate; and sequentially forming an inter-gate dielectric layer and a control gate layer over said substrate.
According a yet further aspect of the invention, there is provided a method for forming a nonvolatile memory device comprising the steps of forming a mask layer on a semiconductor substrate; patterning the mask layer and the substrate to form trenches in the substrate; filling the trenches with isolation oxides that protrude above the substrate; removing the mask layer to leave a gate opening in between the isolation oxides; forming two dielectric spacers on a pair of opposing sidewalls of the isolation oxides, the two dielectric spacers being spaced from one another at a distance that defines a gate width therebetween; forming a tunnel dielectric layer on the substrate and between the two dielectric spacers; forming a floating gate layer on the tunnel dielectric layer and completely filling the gate opening; planarizing the floating gate layer to form a surface substantially coplanar with a surface of the isolation structures; and sequentially forming an inter-gate dielectric layer and a control gate layer on the coplanar surfaces of the floating gate and the two isolation structures.